Phase-locked loops (PLL's) are commonly used to perform a multitude of different functions in electrical and electronic systems. Such functions include tone decoding, demodulation of communication signals, frequency multiplication, frequency synthesis, pulse synchronization, and signal regeneration, for example. In a digital communication system, one application of a PLL may be to provide a "clean" clock signal which has the same frequency and phase as a received digital data signal that is to be decoded. Digital phase-locked loops (DPLL's) are often preferable to analog PLL's for this purpose, because they tend to require less time and effort to design.
One problem associated with DPLL's, however, is that, as a result of their discrete nature, they normally cannot generate an output clock with a phase that is precisely locked to the phase of the input signal. A typical DPLL design makes use of a reference clock having a frequency that is much higher than that of the data signal to generate the output clock. However, a typical DPLL can only guarantee a phase lock to within one clock period of the reference clock. This error in the phase lock is referred to as "jitter". "Jitter" can be more precisely defined as any short-term variations of the significant instances of a digital signal from their ideal positions in time. In addition, a typical DPLL will only adjust its lock once for every clock cycle of the data signal or the output clock (e.g., on every rising edge of the data signal), which limits how quickly the DPLL can lock onto the input signal. Consequently, as design requirements for the maximum allowable jitter (accuracy of the phase lock) and the time-to-lock become more demanding, the required reference clock frequency increases. A high reference clock frequency may be undesirable for various different reasons, however.
Therefore, it is desirable to provide a DPLL which has a maximum jitter that is less than one full period of the reference clock. It is further desirable to provide a DPLL that will adjust its phase lock more frequently than once for each period of the data signal or the output clock, so that the time required to achieve phase lock may be reduced.